1. Field of the Invention
The present invention relates to memory access control technology for controlling access to a plurality of memory devices with differing latency.
2. Description of the Related Art
Conventionally, substrates are designed such that wiring delay between large-scale integrated circuits (LSIs) and memory devices does not exceed one clock cycle of the memory. However, as operating frequencies rise, keeping the wiring delay from exceeding one clock cycle of the memory through substrate design has become difficult, and cases arises in which memory devices have differing access latencies.
Accordingly, memory access control circuits capable of accurately performing data exchange with a plurality of memory devices taking into consideration wiring delay have been considered (e.g., Japanese Patent Laid-Open No. 2003-173290).
FIG. 1 is a block diagram showing one example of a memory access control circuit in a conventional example. As shown in FIG. 1, memory devices 191 and 192 are connected to a memory access control circuit 100, and the memory access control circuit 100 controls access to the memory devices 191 and 192. Note that in the example shown in FIG. 1, DDR-type memory devices are used as the memory devices.
In FIG. 1, 101 is a chip select signal, and is asserted when the memory access control circuit 100 accesses the memory device 191. 102 is a chip select signal, and is asserted when the memory access control circuit 100 accesses the memory device 192.
103 is a clock signal, and is supplied to the memory devices 191 and 192 from the memory access control circuit 100. The memory devices 191 and 192 operate in synch with a clock signal 103. 104 is a command signal, and is issued to the memory devices 191 and 192 from the memory access control circuit 100. The memory devices 191 and 192 receive a command signal 104 when the corresponding chip select signals 101 and 102 are asserted, and perform processes corresponding to the content of the commands.
105 is a two-way data strobe signal. The memory access control circuit 100 and the memory devices 191 and 192 drive the data strobe signal 105 when data is transmitted. 106 is a two-way data signal. When writing, the memory access control circuit 100 drives the data signal 106 at a predetermined timing, and when reading, the memory device 191 or the memory device 192 drive the data signal 106 at a predetermined timing.
In the memory access control circuit 100, 110 is a prior command information holding circuit, and holds information on the command issued immediately before. It is provided internally with a prior access direction buffer 111 for holding the reading or writing direction of the command issued immediately before.
120 is a command information holding circuit, and holds information on the command to be issued next. It is provided internally with an access direction buffer 121 for holding the reading or writing direction of the command to be issued next.
130 is a command interval information holding circuit, and holds information on the minimum command issuing interval from issuing of the prior command to issuing of the next command. It is provided internally with command interval buffers 131a to 131d, and holds the minimum command issuing interval among all combinations of reading and writing directions of the prior command and reading and writing directions of the next command. In other words, in the example shown in FIG. 1, four sets of command intervals are held.
140 is a latency information holding circuit, and holds the read latency and write latency of memory devices corresponding to settings of memory devices connected to the memory access control circuit 100.
150 is a command issuing control circuit, and controls issuing of commands to the memory devices 191 and 192. A command issuing interval selection circuit 151 selects a relevant command interval from the command interval buffers 131a to 131d according to the prior access direction buffer 111 and the access direction buffer 121. Next, a command issuing timing control circuit 152 delays the timing for causing the next command to be issued by the command interval selected by the command issuing interval selection circuit 151.
160 is a data issuing control circuit, and drives the data signal 106 after a time period equivalent to the write latency held in the latency information holding circuit 140 has elapsed since the command issuing control circuit 150 issued a command. 170 is a data reception control circuit, and receives data read from the memory devices 191 and 192.
180 is a memory access interface, and receives memory access requests from external circuits, transmits commands to the command issuing control circuit 150, and sets reading or writing information to the access direction buffer 121.
A method for calculating the command issuing intervals to be set to the command interval buffers 131a to 131d is described below. The calculation method is as laid out in (1) to (4) below.
(1) Issuing a write command and then issuing a write commandCommand issuing interval=data transfer length/2+minimum data interval(2) Issuing a write command and then issuing a read commandCommand issuing interval=prior access device write latency+data transfer length/2+maximum access device wiring delay−next access device read latency−minimum access device wiring delay(3) Issuing a read command and then issuing a write commandCommand issuing interval=maximum access device wiring delay×2+prior access device read latency+data transfer length/2+minimum data interval−next access device write latency(4) Issuing a read command and then issuing a read commandCommand issuing interval=maximum access device wiring delay×2+data transfer length/2+minimum data interval−minimum access device wiring delay×2
If a command is issued without satisfying the command issuing interval calculated using the above calculation method, there is the risk of collision between the driving of the data signals between the memory access control circuit 100 and the memory devices 191 and 192.
Note that read and write accesses between the memory access control circuit 100 and the memory devices 191 and 192 both use four-beat transfers.
The wiring delay between the memory access control circuit 100 and the memory device 191 is assumed to be 0.5 clock cycles, and the wiring delay between the memory access control circuit 100 and the memory device 192 is assumed to be 1.5 clock cycle. The read latency held in the latency information holding circuit 140 is assumed to be 3 clock cycles, and the write latency 2 clock cycles.
As described above, minimum command interval values are calculated based on the access length, the wiring delay, and the latency such that the driving of the data signal 106 by the memory access control circuit 100 and the memory devices 191 and 192 does not collide, and are set to the command interval buffers 131a-d. 
In the conventional example, “data transfer length/2” is 2 clock cycles, since only four-beat memory access is handled. Further, the “minimum data interval” is the interval for preventing data which is continuously accessed from being contiguous in the data signal, and is ordinarily one clock cycle.
When the command issuing intervals are calculated using the above command issuing interval calculation method, the result is as follows. Namely, the following intervals (clock cycles) are set to the command interval buffers 131a to 131d, and clock cycles equal to at least those intervals are placed between commands.
(1) Issuing a write command and then issuing a write command (131a): 3 clock cycles
(2) Issuing a write command and then issuing a read command: 2 clock cycles
(3) Issuing a read command and then issuing a write command: 7 clock cycles
(4) Issuing a read command and then issuing a read command: 5 clock cycles
Operation in a case in which the memory access control circuit 100 issues a read command to the memory device 192 and then issues a write command to the memory device 191 (operation example 1) is described now, with reference to FIG. 2.
FIG. 2 is a timing chart showing operation example 1 when issuing a command in the conventional example. In FIG. 2, the waveform marked as the memory access control circuit 100 is the waveform obtained by sampling the signal pin of the memory access control circuit 100. CLK, CS0, CS1, and CMD are output signals of the memory access control circuit 100, and DQS and DQ are input/output signals of the memory access control circuit 100.
The memory device 191 and the memory device 192 are waveforms obtained by sampling the signal pins of the memory devices. CLK—0, CS—0, and CMD—0, and CLK—1, CS—1, and CMD—1 are input signals of the memory devices, and DQS—0 and DQ—0, and DQS—1 and DQ—1 are input/output signals of the memory devices.
Information is set to the access direction buffer 121 by a memory access interface 180 to the effect that the next command is a read command. When the access direction buffer 121 is set, the command issuing interval selection circuit 151 notifies the command issuing timing control circuit 152 that there are 0 cycles until command issue is possible, since the prior access direction buffer 111 is empty.
On the other hand, the command issuing timing control circuit 152 receives the information that there are 0 clock cycles until command issue, and puts out a command issue permit after 0 clock cycles. The command issuing control circuit 150 asserts the chip select signal 102 and issues a read command (T3).
The command issuing control circuit 150 issues the command, and at the same time sets the information of the access direction buffer 121, indicating reading, to the prior access direction buffer 111. At the same time, the memory access interface 180 sets information to the access direction buffer 121 that the next command is a write command.
The read command issued by the command issuing control circuit 150 is received by the memory device 192 after a delay of 1.5 clock cycles (B4). Since the received command is a read command, the memory device 192 drives the data signal 106 after a read latency of 3 clock cycles has elapsed (B7). The data driven by the memory device 192 is received by the data reception control circuit 170 after a delay of 1.5 clock cycles (T10 to T12).
Since the prior command is a read command and the next command is a write command, the command issuing interval selection circuit 151 selects the command interval buffer 131c. The command issuing timing control circuit 152 is therefore notified that there are 7 clock cycles until command issue is possible.
The command issuing timing control circuit 152 receives the information that there are 7 clock cycles until command issue, and puts out a command issue permit after 7 clock cycles, starting from the issuing of the prior command (T3).
The command issuing control circuit 150 asserts the chip select signal 101 and issues a write command (T10). The command issuing control circuit 150 issues the command, and at the same time sets the information of the access direction buffer 121 to the prior access direction buffer 111.
The write command issued by the command issuing control circuit 150 is received by the memory device 191 after a delay of 0.5 clock cycles (A11). The data issuing control circuit 160 drives the data signal 106 after the write latency of 2 cycles held by the latency information holding circuit 140 has elapsed from the timing at which the command issuing control circuit 150 issued the write command (T13). The data issued by the data issuing control circuit 160 is received by the memory device 191 after a delay of 0.5 clock cycles (A13 to A15).
Next, operation in a case in which the memory access control circuit 100 issues a read command to the memory device 191 and then issues a write command to the memory device 192 (operation example 2) is described now, with reference to FIG. 3.
FIG. 3 is a timing chart showing operation example 2 when issuing a command in the conventional example. Note that the sampling points for the waveforms shown in FIG. 3 are the same as those in FIG. 2.
Information is set to the access direction buffer 121 by a memory access interface 180 to the effect that the next command is a read command. When the access direction buffer 121 is set, the command issuing interval selection circuit 151 notifies the command issuing timing control circuit 152 that there are 0 cycles until command issuing is possible, since the prior access direction buffer 111 is empty.
On the other hand, the command issuing timing control circuit 152 receives the information that there are 0 clock cycles until command issue, and puts out a command issue permit after 0 clock cycles. The command issuing control circuit 150 asserts the chip select signal 101 and issues a read command (T3).
The command issuing control circuit 150 issues the command, and at the same time sets the information of the access direction buffer 121, indicating reading, to the prior access direction buffer 111. At the same time, the memory access interface 180 sets information to the access direction buffer 121 that the next command is a write command.
The read command issued by the command issuing control circuit 150 is received by the memory device 191 after a delay of 0.5 clock cycles (A4). Since the received command is a read command, the memory device 191 drives the data signal 106 after a read latency of 3 clock cycles has elapsed (A7). The data driven by the memory device 192 is received by the data reception control circuit 170 after a delay of 0.5 clock cycles (T8 to T10).
Since the prior command is a read command and the next command is a write command, the command issuing interval selection circuit 151 selects the command interval buffer 131c. The command issuing timing control circuit 152 is therefore notified that there are 7 clock cycles until command issue is possible. The command issuing timing control circuit 152 receives the information that there are 7 clock cycles until command issue, and puts out a command issue permit after 7 clock cycles, starting from the issuing of the prior command (T3).
The command issuing control circuit 150 asserts the chip select signal 102 and issues a write command (T10). The command issuing control circuit 150 issues the command, and at the same time sets the information of the access direction buffer 121 to the prior access direction buffer 111.
The write command issued by the command issuing control circuit 150 is received by the memory device 192 after a delay of 1.5 clock cycles (B11). The data issuing control circuit 160 drives the data signal 106 after the write latency of 2 cycles held by the latency information holding circuit 140 has elapsed from the timing at which the command issuing control circuit 150 issued the write command (T13). The data issued by the data issuing control circuit 160 is received by the memory device 192 after a delay of 1.5 clock cycles (B13 to B15).
Only operation in a case of reading and then writing has been described, but cases of writing and then writing, writing and then reading, and reading and then reading are the same. In other words, relevant information is selected from the command interval buffers 131a to 131d by the command issuing interval selection circuit 151, and the command issuing timing control circuit 152 puts out an issuing permit according to the selected information. Data transfer is performed without driving of the data signal 106 colliding, since the command issuing control circuit 150 issues commands.
However, if the command issuing interval is controlled based on the reading/writing information of the prior command and the reading/writing information of the next command, there is a need to wait the command issuing interval to match the access to the memory device with the highest access latency.
A situation can arise in which data signals are not driven due to excessive gaps in the command issuing intervals, even when accessing memory devices with low access latency. For example, in the relevant art example above, in FIG. 3 memory access can be performed with no collision of the driving of the data signal 106 even if the writing command issued by the memory access control circuit 100 were issued 2 clock cycles earlier (T8).
Accordingly, a problem arises in that unnecessary transfer intervals are wasted during cycles in which data transfer is possible, lowering usage efficiency of the memory bus.